While shrinking the package a dice when you try to improve its performance simultaneously then it is known as an act of Advanced Packaging. The information provided here under will help you to know about different Advanced Packaging Solutions.
The circuit board of a Smartphone with a number of black small rectangles can be the best example to understand Advanced Packaging. If you have ever opened the body of your Smartphone then you will find packaged chips in the form of black rectangles. The external structure of these chips protects the delicate IC inside it along with isolate the chip from other chips and disperses heat along with connecting the circuit board with other parts of the phone. So, the steps used collectively in creating these connections and protective structures during the manufacturing of a Smartphone are known as packaging. The combination of powerful and smaller chips and packaging has made radical changes in the world of electronics during the last few years.
Some of the strategies used for developing advanced packaging solutions of the next generation are briefly discussed here under to help you in understanding them more precisely.
Flip chips and bumping
The connection between the circuit board and a chip can be one of the easiest electrical connections by using bumps, electrically conductive small balls. These bumps can connect with suitable pads n the board when the bumped die is overturned by flipping and aligned. The bonding of the flip-chip can be very beneficial as compared to traditionally used bonding with wire because of its high speed and small size of the package.
By increasing the use of the conventional method of wafer fabrication bumping can be performed. UBM pads or under bump metallization pads are created after making the chips to connect the circuit of the chip so that pads can be used to put down bumps. Though copper, cobalt, or gold can be used as a bumping material but solder is normally used for this purpose, depending upon the applications you are using it on. Copper pillars can be used for connecting applications with fine pitch or interconnections of high density. During the process of joining the bumps of the solder can spread whereas the shape of the copper pillar will remain the same and allow them to put them together more closely.
A finished wafer is diced or cut into pieces in the conventional methods of packaging to encapsulate and bond them. This process is known as WLP or Wafer-level packaging due to the involvement of wafer while packaging the die. On the bottom and top of the wafer protective layers can be bonded to prepare electrical connections and cutting the wafer into various chips. It is just like frosting cupcakes individually, if compared with technologies used in a bakery. In this process, WLP is sliced into pieces as done in frosting a cupcake. The size of the resultant chips remains small because its sides are not coated with WLP. They can be used in devices with sensitive footprints like Smartphones. Testing the functionality of the chip before cutting it into dices and streamlining the manufacturing process can be other benefits of this advanced packaging solution.
Though the surface area used by chips on the circuit board can be reduced using bumping but you can use this area more efficiently by stacking the chips. The performance of several chips can be improved by stacking them. The chips can be assembled and stacked by using wire bonding but Through-Silicon Vias or TSVs can be a better alternative to it as it can form a smaller stack. Being an electrical connection through the thickness of the chip, a TSV can create the direct path to reach from side to side of the chip which can provide larger bandwidth with lower consumption of power.
TSVs can commonly be created by etching the holes or vias to a certain depth of the wafer from its front side. They are isolated and filled with copper, a conductive material. After completing the creation of a chip, vias are exposed by thinning the wafer from the backside and it completes interconnection with the help of the metal deposited on the back of the wafer.
When you need more contact points but the size of the chip becomes smaller then to fan-out or spread the connection points, the redistribution process can be used. Spreading or fanning-out the contacts away from the size of the chip can be one of the solutions for it. It can improve the performance of thermal and electrical devices by reducing the height of the overall package.
The process of FOWLP of fan-out wafer-level packaging includes cutting the processed wafer into several dices which are put apart on the structure of a carrier to form a reconstituted wafer by filling the gaps. The contacts can be distributed again beyond the edges of the dice by using the process of WLP, after building the reconstituted wafer.
Another technique that can be used at the wafer-level efficiently is redistributing to relocating contact points. RDL or redistribution layers can be used to change the route of the connection to the locations desired by them. For instance, the collection of bumps at the center of the chip can be relocated to near its edge. The density of contacts can be increased and successive steps of packaging can be taken by being able to redistribute the points. This process can be known as a fan-in process as it helps in creating the smallest package.
In this process, one more set of layers is added on the surface of the wafer and for electrical isolation, a dielectric film is deposited to expose the original bond pads. To relocate the pads to the locations desired by them metal lines are deposited and to support bumps of solder under bump metallization layers are added.
Thus, various types of strategies discussed in this write-up to develop advanced packaging solutions can help you in choose the most suitable one for packaging any electronic application.