The competition in the semiconductor industry is becoming fiercer by the day. As such, the importance of the packaging process is being highlighted as a way to implement even smaller and thinner semiconductors with high performance and low power consumption, while simultaneously responding to the limitations of semiconductor miniaturization technology and other market demands.
Packaging is the process where the manufactured semiconductors are packaged so that they are not damaged, with electric wires in semiconductor circuits connected to the outside. Previously, this process was generally recognized as simple and auxiliary work since it was done during the back-end process where the manufactured semiconductors were shipped, rather than the front-end process when semiconductor quality was determined. Recently, however, as the feature size of transistors decreases to 5nm or less and the growing possibility that semiconductor manufacturing will face physical limitations within the next few years, the packaging technology is attracting more attention than ever.
SK hynix has a sense of mission that the packaging process is a key one that’s closely connected to customers and represents a semiconductor product. Under this mission, the company aims to create the best performance and quality.
In this article, we will explore packaging technology in detail and learn about its future.
Rethinking packaging technology
Figure 1. The evolution of packaging technology
Figure 2. Variations in FOWLP technology include die-first and RDL-first assembly options (Source: Micromachines via EE Times)
With the continuous demand for high performance and high capacity in memory products, technologies such as *redistribution layer (RDL), *flip chip, and *through-silicon via (TSV) have been actively used in packages from a decade ago [Figure 1]. These technologies break away from the conventional method of packaging at the chip level and perform the process in a silicon (Si) wafer or in a wafer where chips are stacked, which dramatically improves product performance and capacity. In particular, SK hynix is leading the market with an industry-leading TSV stacking technology, such as high bandwidth memory (HBM), which is an in-package memory solution, as well as three-dimensional stack (3DS), which is a high-density memory (HDM) for servers [Figure 2]. In 2016, for the first time ever, SK hynix applied the *mass reflow method where four 50-um thick chips were placed one after the other and bonded at once to TSV stacking technology, succeeding in developing a 3DS memory for servers. The company recently applied this technology to the 8-layer stacking of HBM. By employing multiple thermal dummy bumps to serve as a heat dissipation path and using a mold material with excellent thermal conductivity as a gap-fill material, SK hynix has dramatically improved the heat generation issue caused by the increase in memory bandwidth while simultaneously lowering the high cost of TSV manufacturing significantly.
Figure 3. Memory product using TSV technology
<Footnote>
*Redistribution Layer (RDL): Rewiring technology; RDL technology aims to rearrange pads already formed on a wafer to re-form them at a desired location by forming an additional metal layer.
*Flip chip: A method of inverting and bonding a chip by utilizing a small bump called a solder ball with a size of several tens of micrometers (㎛) protruding on the pad of a chip
*Through-silicon via (TSV): A method of 3D stacking multiple chips vertically after forming a through-electrode by drilling a hole (via) inside the silicon chip; when using this method, the packaging area is smaller, and more chips can be stacked in the same thickness compared to the connection method using wires. Also, as this method can connect multiple I/Os in the shortest distance, high bandwidth and reduced power consumption can be realized. (Please refer to the related article here.)
*Mass reflow molded underfill (MR-MUF): A method of placing multiple chips on the lower substrate and bonding them at once through reflow, and then simultaneously filing the gap between the chips or between the chip and the substrate with a mold material, mainly in flip chip and TSV chip stacking methods.
Memory Capacity Demands Impact Chip Technology
The TSV technology used in HBM is a method of vertically stacking multiple chips – four to eight chips, in general – using silicon through-hall electrodes (TSV) and micro bumps. Due to the continuous demand for high capacity in memory products, multi-chip stacking technology of 12 to 16 layers or even higher is expected to be required in the future. To get there, not only must the thickness of chip and the size of the bump electrodes be reduced, but the *hybrid bonding technology that removes the filler between chips to directly connect to copper (Cu) electrodes will need to be applied in the near future [Figure 3].
Figure 4. Schematic diagram of vertical lamination using micro bump and hybrid bonding
The hybrid bonding method can significantly reduce the electrode size, compared to the method using micro bumps, and thereby increase the number of I/Os per unit area, which dramatically reduces power consumption. At the same time, this method can realize a high-capacity package by significantly minimizing the gap between chips. It also improves the heat dissipation characteristics, effectively solving the heat generation issue caused by the increase in power consumption.
*Hybrid bonding: A method of simultaneously bonding a metal electrode such as a copper (Cu) electrode and inorganic insulating layer; As a method of integrating at least two different chips into one package, it can reduce the interconnection pitch and it is expected to be widely used for vertical stacking of multiple system on a chip (SoC) dies, SoC-memory, and memory.
Balancing Capacity and Heat Generation
In addition to the innovation of TSV technology as it relates to capacity, there is a need for a high-speed chip and a *heterogeneous integration solution of memory chips that can maximize the characteristics of memory products within a system. There is also a need for a new packaging solution to overcome the heat generation issue caused by the increase in power of memory chips and the thickness limit created by the increased number of stacked memory chips. *Fan-out wafer-level packaging (Fan-out WLP) is a technology that relocates I/O pads of a chip to the outer area of the chip by using the wafer-level rewiring technology. As an advanced packaging technology, it is now actively applied to non-memory chips such as application processors (APs) and power management integrated circuits (PMICs). In this technology, the thickness of a package can be reduced by using a redistribution layer to replace a substrate. Because that can improve the heat dissipation effect, the application of this technology to memory products also is being actively studied.
Figure 5. Schematic diagram of fan-out WLP
In addition, to solve the tech shrinkage limitation and power budget issue of memory devices, integration with heterogeneous chips, other than memory chips, is being actively studied. This can be implemented in various forms of packages through the fan-out technology, which not only improves the performance of memory products, but also enables expandability through new applications [Figure 4]. The fan-out technology can be converged with various packaging technologies including wire bonding, TSV, redistribution, and bump technology, and can be implemented as a package of various forms of memory products. It is the key technology to implement a fan-out WLP structure capable of vertical stacking since memory chips require sufficient capacity. Ensuring the electrical characteristics and quality of wiring is the key because it is essential for the fan-out WLP of memory products to vertically connect the fan-out RDL wiring from the I/O of several stacked chips, in addition to the general fan-out RDL technology.
<Footnote>
*Heterogeneous Integration Solution: A method of implementing different types of (heterogeneous) devices in one package
*Fan-out wafer-level packaging (Fan-out WLP): It refers to a process of forming a ball terminal for external connection in the outer area by expanding a chip. By eliminating the need for a PCB substrate, a thinner package can be implemented, and the cost of PCB substrates can be saved. Since this method makes it easier to bridge heterogeneous chips in the horizontal direction through redistribution, it can be used in multi-functional and high-performance memory systems.
Transforming Packaging for Growth
Research has found that 3D stacking technology using TSV and fan-out technology are expected to show annual growth rates of around 20% and 15%, respectively. As this suggests, it can be said that these are representative technologies in advanced packaging. Both the TSV and fan-out WLP technologies are evolving to address the various limitations of current memory products. In the past, packaging technology has contributed greatly to the added value of memory products. As such, SK hynix will continue to transform and specialize advanced packaging technologies for each memory product for more innovation, actively responding to market demands.
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